1. Field of Invention
The present invention relates to a gate circuit which is operated at high speed with low consumption power by low amplitude operation signals of the semiconductor integrated circuit device, and more particularly to a semiconductor memory device or semiconductor memory circuit device characterized by high speed and high integration, and an information processing system provided with these circuits or devices.
2. Description of the Prior Art
A first prior art circuit is described in Japanese Patent Laid-Open NO. 61-293018 and Japanese Patent Laid-Open 62-186613. FIG. 18 is a sketch of this first prior art circuit.
According to this first prior art circuit, when the output signal 1809 of NMOS transistor (hereinafter referred to as xe2x80x9cNMOSxe2x80x9d) 1806 is high, namely, (power potential)xe2x80x94(NMOS threshold voltage), the PMOS transistor (hereinafter referred to as xe2x80x9cPMOSxe2x80x9d) 1810 prevents the breakthrough current of inverter 1812 from flowing and stabilizes the potential of output signal 1813.
Second prior art circuit are described in Japanese Patent Laid-open NO. 62-32722 and Japanese Patent Laid-open NO. 63-5172. FIGS. 19 and 20 are sketches of these second prior art circuits.
With reference to FIG. 19 illustrating one of the second prior art circuits, PMOS Q3 is a transistor for driving transistor when signals are applied to the gate from terminal 1905, in order to drive PMOS transistor Q1 if the input signal 1901 is high. When the input signal is low, transistor Q3 turns off and operates in such a way that the high level at point A will be applied to the NMOS transistor Q2 gate, without being applied to the gate of Q1, thereby serving to increase the switching speed between Q1 and Q2.
Similarly, when input signal 1901 is high, the level at point A is low in FIG. 20. NMOS transistor Q12 is off and NMOS Q14 is on; therefore, the level at point B is also low. Accordingly, PMOS transistor Q13 is turned to drive the NMOS transistor Q11. When the input signal 1901 is low, the level at point A is high, and NMOS Q14, PMOS Q13 and NMOS Q11 are turned off. After the NMOS Q12 turns on, the output signal level turns low. At this time, all the Q11, Q13 and Q14 are turned off; therefore, almost no current runs from the 2003.
That is, transistor Q14 functions as a switching element to switch the pull-down circuit and the pull-up circuit.
A third prior art circuit widely known as the memory cell circuit used in the CMOS gate array LSI in conventional semiconductor memory device, includes the circuit used for the memory unit of a 1W-1R (one-port write-in, one-port read-out), or that used for the memory unit of a 2W-2R (two-port write-in, two-port read-out). The data memory unit of the former is composed of a CMOS inverter and a clocked inverter. The data write-in side of the data memory unit is linked to the write data line through a pair of transfer gates, and the data read-out side is linked to the read data line through the clocked inverter. Each clocked inverter comprises two PMOS transistors and two NMOS transistors, and the entire memory cell circuit is made up of six PMOS transistors and six NMOS transistors.
The data memory unit of the latter, on the other hand, comprises a pair of clocked inverters, and the data write-in side of the data memory unit is linked to the write data line through a pair of transfer gates, while the data read-out side is linked to the read data line through the read-out clocked inverter. Each clocked inverter comprises two PMOS transistors and two NMOS transistors, and the transfer gate is made up of one PMOS transistor and one NMOS transistor. The entire memory cell circuit is made up of ten PMOS transistors and ten NMOS transistors.
The first prior art circuit has associated there with the following problem: When the potential of the clocked inverter 1809 of the NMOS transistor 1806 is high, breakthrough current flows to the inverter 1912 until feedback is applied by MOS transistor 1810.
This is because the high level of the output signal 1809 of NMOS transistor 1806 is reduced below the power potential by the threshold voltage of the NMOS transistor 1806.
Also first prior art circuit the following is at issue: When the potential of the output signal 1809 of NMOS transistor 1806 is reduced from a high to a low level, the potential must be changed from the power source potential to the grounding potential, and this takes more time than the time required to change from the high level of the intermediate potential (potential reduced from power supply potential by threshold voltage of NMOS transistor 1806) to the grounding potential.
The above recognized problem is caused by the PMOS transistor 1810, provided to avoid breakthrough current of the inverter 1812.
Unlike the circuit according to the present invention, the second prior art circuit provides a circuit where a high voltage circuit is driven by a low voltage CMOS circuit to produce high voltage signals.
This requires two or more different power supply voltages to be provided, resulting in a complicated structure of the power supply system.
Furthermore, according to the second prior art circuit, signals at point A are driven by the complementary circuit comprising transistors Q4 and Q5, and the potential at point A provides the same amplitude as that of the power supply voltage. Accordingly, the complementary circuit comprising transistors Q4 and Q5 has little effect in reducing power consumption since it reduces the charging and discharging current at point A. Furthermore, operation amplitude at point A is the same as that of power supply voltage, so it is less effective in increasing speed by reducing signal amplitude. Moreover, when the level o input signal 1901 is high, direct current will flow through R1, Q3 and Q4, and R1, Q14 and Q4, resulting in increased power consumption.
In the third prior art circuit, each six or ten PMOS transistors and six NMOS transistors are used to configure the memory cell circuit. When the basic cell is made up of two pairs of two-series PMOS transistors and two-series NMOS transistors (eight transistor in total), for example, the former requires a minimum of 1.5 BCs (basic cells), while the latter requires a minimum of 2.5 BCs (basic cells), resulting in increased area of the memory cell circuit. The read data line is linked to a read-out clocked inverter for each memory cell, and the read data line must be provided with an additional drain capacity for two transistors of the clocked inverter; PMOS transistor and NMOS transistor, causing the read data line load capacity and the memory access time to be increased.
One object of the present invention is to provide a semiconductor integrated circuit which operates at low power consumption from a single power supply without any breakthrough current, despite reception of input signals of low amplitude operation.
Another object of the present invention is to provide a semiconductor integrated circuit device where the input signal transition time is shortened by reducing the amplitude of input signals, and power consumption in a driver circuit to drive said input signals is reduced.
Still another object of the present invention is to provide a semiconductor memory device characterized by high speed and low power consumption, plus high memory density of the master slide type LSI such as gate array and embedded array.
A further object of the present invention is to provide a semiconductor integrated circuit device and semiconductor memory device, which allow reduction of the capacity to be added to the data line.
In the present invention, input signals are fed to a first NMOS transistor, and to a gate of a first PMOS transistor which performs a complementary operation with the first NMOS transistor through a second NMOS transistor. The gate of the first PMOS transistor is linked to the power supply potential through a second PMOS transistor, and the gate of the second NMOS transistor is linked to the power supply potential. The first NMOS transistor drain and said first PMOS transistor drain are commonly connected to the second PMOS transistor gate. Thus, in the present invention, control is provided by the signals fed through the said procedure.
When applied to the memory, another characteristic of the present invention is found as follows: The read-out port is single-ended, and the switch, which is turned on or off by the read-out word line level, is made of a single NMOS or PMOS transistor, not a clocked inverter.
Since the read-out switch is made of a single NMOS or PMOS transistor, the current drive force of the circuit of the gates which configure the memory cell memory unit and which drive the read data line is increased in order to avoid writing errors at the time of reading. The write-in port is designed to permit differential write-in or single end write-in. Since the read-out switch is made of a single NMOS or PMOS transistor, it is provided with the signal receiving circuit to feedback its own output signal and to control the pull-up MOS, in order to ensure that leak current will not flow in the circuit receiving the signal of the read data line, even if the read data line does not provide a full amplitude. The number of the transistors used in the memory cell circuit is determined in the case of the memory made up of the basic cells of the gate array , namely, the metallized memory, such that the number of PMOS transistors and the number of NMOS transistors will be equal to each other in order to eliminate any unwanted surplus.
To achieve the above stated objects, the present invention provides a semiconductor integrated circuit device having a single-ended, read-out port configuration. The device comprises: (1) a data memory unit wherein two or more inverter circuits are made up of two or more semiconductor elements, and each inverter circuit is connected to the other to configure a data memory closed loop, (2) a data input unit wherein the data memory unit is connected to the write data line by a write data transmission channel, which is opened or closed in response to the write-in signal by said data input unit, (3) a data output unit wherein the data memory unit is connected to the read data line by a read data transmission channel, which is opened or closed in response to the read-out signal by said the data output unit, and (4) a loop control unit, which opens the closed loop of the data memory unit at the time of data writing in response to the write-in signal and to close the closed loop of the data memory unit after writing the data; the data output unit being made up of a single MOSFET.
The semiconductor integrated circuit device having a singleended write-in port configuration comprises: (1) a data memory unit wherein two or more inverter circuits are made up of two or more semiconductor elements, and each inverter circuit is connected with the other to configure a data memory closed loop, (2) a data input unit wherein said data memory unit being connected to the write data line by a write data transmission channel, which is opened or closed in response to the write-in signal by said data input unit, (3) a data output unit wherein the data memory unit is connected to the read data line by a read data transmission channel, which is opened or closed in response to the read-out signal by said data output unit, and (4) a loop control unit which opens the closed loop of the data memory unit at the time of data writing in response to the write-in signal and to close the closed loop of the data memory unit after writing the data; wherein the data input unit is made up of a single MOSFET.
When configuring the said semiconductor integrated circuit, the read-out port and write-out port can each be made single-ended if each of the data input unit and data output unit is made up of a single MOSFET.
Next, the semiconductor integrated circuit device with consideration given to differential write-in operation comprises: (1) a data memory unit wherein two or more inverter circuits are made up of two or more semiconductor elements, and each inverter circuit is connected to the other to configure a data memory closed loop, (2) two or more data input units wherein the data memory unit being connected to two or more write data lines by a group of write data transmission channels, which are opened or closed in response to the write-in signal by said data input units, (3) a data output unit wherein the data memory unit is connected to the read data line by a read data transmission channel, which is opened or closed in response to the read-out signal by said data output unit; the data output unit being made up of a single MOSFET. In the configuration of this device, the data input unit can be made up of a single MOSFET, or in the alternative the data input unit and data output unit can each be made up of a single MOSFET.
Next, the semiconductor integrated circuit device) with consideration given to two-port write-in, two-port read-out;comprises: (1) a data memory wherein two or more inverter circuits are made up of two or more semiconductor elements, and each inverter circuit is connected to the other to configure a data memory closed loop, (2) two or more data input units wherein said data memory unit being connected to the write data line by two or more write data transmission channels, which are opened or closed in response to the write-in signal by said data input units, (3) two or more data output units wherein the data memory unit is connected with the read data line by two or more read data transmission channels, which are opened or closed in response to the read-out signal by said data output units, and (4) a loop control unit which opens the closed loop of each data memory unit at the time of data writing in response to the write-in signal and to close the closed loop of the data memory unit, after writing the data; the data input units each being made of a single MOSFET. In configuration of this device, the data input unit can be made up of a single MOSFET, or alternatively the data input unit and data output unit can each be made of a single MOSFET.
In configuration of this device, of the inverter circuits of the data memory unit, those connected to the read data line through the data output unit when reading out the data are preferred to have the output impedance smaller than other inverter circuits.
In configuration of this device, it is preferred that the device has data memory units for two or more bits, with one data memory unit as the data memory area for one bit, and units related to the input and output of the data of each data memory unit be each provided for two or more bits. It is further preferred that the MOSFET group connected to the read data line be divided for each adjacent pair of MOSFETs, and the output terminal of each pair of the MOSFETs be formed in the common area adjacent to the read data line.
Next, the semiconductor integrated circuit device having memory circuits for two or more bits with the single-ended read-out port comprises (1) a data memory unit wherein two or more inverter circuits are made of two or more semiconductor elements, and each inverter circuit is connected to the other to configure a data memory closed loop, (2) a data input unit wherein said data memory unit being connected to the write data line by a write data transmission channel, which is opened or closed in response to the write-in signal by said data input unit, (3) a data output unit wherein the data memory unit is connected to the read data line by a read data transmission channel, which is opened or closed in response to the read-out signal by said data output unit, and (4) a loop control unit which opens the closed loop of the data memory unit at the time of data writing in response to the write-in signal and to close the closed loop of the data memory unit after writing the data. With this configuration equivalent to one bit, the units are provided for two or more bits, and the data memory unit, data input unit, data output unit and loop control unit are each made up of a MOSFET, with the data output unit being composed of a single MOSFET. In the configuration of this device, the data input unit can be composed of a single MOSFET, or alternatively the data input unit and the data output unit can each be made of a single MOSFET.
Next, the semiconductor integrated circuit device having memories for two or more bits with differential write-in taken into account comprises: (1) a data memory unit two or more inverter circuits are made of two or more semiconductor elements, and each inverter circuit is connected to the other to configure a data memory closed loop, (2) two or more data input units wherein the data memory unit is connected to two or more write data line by a group of write data transmission channels, which is opened or closed in response to the write-in signal by said data input units, (3) a data output unit wherein the data memory unit is connected to the read data line by a read data transmission channel, which is opened or closed in response to the read-out signal by said data output unit. With this configuration equivalent to one bit, this units are provided for two or more bits, and the data memory unit, data input unit, and data output unit are each made up of a MOSFET, with the data output unit being composed of a single MOSFET. In the configuration of this device, the data input unit can be composed of a single MOSFET, or the data input unit and the data output unit can each be made of a single MOSFET.
Next, the semiconductor integrated circuit device having memories for two or more bits with two-port write-in and two-port read-out taken into account comprises: (1) a data memory unit wherein two or more inverter circuits are made of two or more semiconductor elements, and each inverter circuit is connected to the other to configure a data memory closed loop, (2) two or more data input units wherein said data memory unit is connected to the write data line by two or more write data transmission channels, which are opened or closed in response to the write-in signal by said input units, (3) a data output unit wherein the data memory unit is connected to the read data line by a read data transmission channel, which is opened or closed in response to the read-out signal by said data output unit, and (4) a loop control unit which opens the closed loop of the data memory unit at the time of data writing in response to the write-in signal and to close the closed loop of the data memory unit after writing the data. With this configuration equivalent to one bit, the units are provided for two or more bits, and said data memory unit, data input unit, data output unit and loop control are each made of a MOSFET, with said data output unit being composed of a single MOSFET. In the configuration of this device, the data input unit can be composed of a single MOSFET, or the data input unit and the data output unit can each be made of a single MOSFET.
When configuring the device with consideration given to memories for two or more bits, of the inverter circuits of the data memory unit, those connected to the read data line through the data output unit when reading out the data are preferred to have the output impedance smaller than other inverter circuits.
In configuring the device with consideration given to memories for two or more bits, of the inverter circuits of the data memory unit, those connected to the read data line through the data output unit when reading out the data are preferred to be composed of two or more P type MOSFET and a single N type MOSFET, and each P type MOSFET is preferred to be parallel connected with the other.
When configuring the memories for two or more bits, it is preferred that the MOSFET group linked to the read data line be divided for each adjacent pair of MOSFETs, and the output terminal of each pair of the MOSFETs be formed in the common area adjacent to the read data line.
Furthermore, when configuring the device with memories for two or more bits taken into account, it is By preferred that the device be composed of: (1) a first P type MOSFET and a first N type MOSFET which are provided with a level shift unit to shift a level of a read data line signal between a read data line and a read data output terminal to output it to the read data output terminal, the level shift unit being inserted between the read data line and read data output terminal to configure the inverter circuit, (2) a second N type MOSFET connected to the gate power supply terminal by the source drain path formed between the gate of the first P type MOSFET and the read data line, (3) a second P type MOSFET where the gate is grounded by the source drain path formed between the power supply terminal and the gate of the first P type MOSFET, and (4) a third P type MOSFET where the gate is connected to the read data output terminal by the source drain path formed between the first P type MOSFET gate and second P type MOSFET source drain path. It is further preferred that the first N type MOSFET gate be connected to the read data line, part of the first N type MOSFET source drain path be grounded, and part of the first P type MOSFET source drain path be connected to the power supply terminal.
According to a first characteristic, the gate of the first NMOS transistor has a low level, and turns off when the input signal level is low. At the same time, input signal is fed to the gate of the first PMOS transistor through second NMOS transistor, causing the first PMOS transistor to be turned off. As a result, the drain potential which is a gate signal of the second PMOS transistor and which is commonly linked to the first NMOS transistor and the first PMOS transistor goes high, causing the second PMOS transistor to be turned off. This requires, however, that the impedance when shifting to the low level the gate potential of the first PMOS transistor be sufficiently lower than that of the second PMOS transistor.
When input signal level is high, the first NMOS transistor turns on since the gate level is high. At the same time, input signal is fed to the first PMOS transistor gate through the second NMOS transistor. However, the potential does not rise to the power supply potential; therefore, the first PMOS transistor does not turned off completely. When the drain commonly connected to the first NMOS transistor and the first PMOS transistor goes closer to the low level, however, the second PMOS transistor will actuate the feedback circuit, and the first PMOS transistor turns off as a result of the gate potential rising to the power supply potential.
It is further possible to ensure a semiconductor integrated circuit which operates at a low power consumption without DC breakthrough current even when the high level of said input signal is intermediate.
Furthermore, it is possible to reduce the power consumption the driver circuit which drives the input signal and to increase the speed by reducing the amplitude of input signal.
The greater the input signal load capacity, the more conspicuous will be these effects.
According to the second characteristic of the present invention, if the memory is configured so that the read-out port is single-ended, and the switch which is turned on or off by the read-out word line level is made of a single NMOS or PMOS transistor, not a clocked inverter, then it is possible to reduce the number of the transistors used in the memory cell circuit and to decrease the load capacity applied to the read data line, resulting in ensuring a high speed access.
The read-out switch is made of a single NMOS or PMOS transistor, and the potential of the read data line will affect the memory cell. However, writing errors in reading can be prevented by raising the current drive force of the gate circuit which configures the memory cell storage unit drives the read data line. The write-in port is designed to permit differential write-in or single end write-in.
In the case of the memory made up of the basic cells of the gate array , namely, the metallized memory, the number of the transistors used in the memory cell circuit can be determined to provide an effective configuration and to eliminate the excessive number of the MOS transistors of the basic cell, by ensuring that the number of PMOS transistors and that of NMOS transistors will be equal to each other.
In the present invention discussed above, the read-out port is designed single-ended, so the data output unit can be made up of a single MOSFET. Since the write-in port is single ended, the data input unit can be made up of a single MOSFET, thereby reducing the number of transistors constituting the memory cell circuit and decreasing the load capacity applied to the read data line or write data line, resulting in ensuring a high speed access.
Furthermore, when the read-out port is composed of a single MOSFET, the read data line potential affects the memory cell when the data is read out. However, to raise the current drive force, it is possible to configure so that the inverters constituting the data memory unit and driving the read data line have a smaller output impedance that other inverters. It is also possible to prevent the inverter value from being reversed by the data line potential when the data is read out, since PMOSFETs are connected in parallel in some of the CMOS inverters. When the device is designed with consideration given to differential writing, the present invention allows the data to be written from the write-in port. Furthermore, when a metallized memory is configured, the present invention provides an effective configuration, and to eliminate the excessive number of the MOS transistors of the basic cell, by ensuring that the number of PMOS transistors and that of NMOS transistors will be equal to each other.